Admissions Open
Admissions Open
The planned work targets to realize load balancing by letting every node to allocate the scalar data and multimedia data among parent nodes, in order to increase packet transfer rate and to decrease the end-to-end delay by estimating the remaining battery status and buffer usage of bottleneck parent nodes. Depending on current buffer usage and the data extents to be delivered by parent node, the required memory banks can be activated. Our proposal will greatly alleviate the packet loss problem, thereby achieving significant reduction in end-to-end delay for packet transfer.