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VLSI DESIGN flow and its FPGA Implementation

Department of Electronics & Communication Engineering, MMEC, MM(DU), Mullana organized as Expert talk on “VLSI DESIGN flow and its FPGA Implementation using Verilog” by Mr Vivek Sheel Dutt (Manager) and Mr. Nitin Tiwari (Design Engineer) from DKOP Labs Pvt Ltd, Noida on August 26, 2015.

OUR CONTACT

  • Maharishi Markandeshwar (DEEMED TO BE UNIVERSITY) Mullana, Ambala (Haryana)
  • +91-1731-274475, 76, 77, 78 | Toll Free: 1800 2740 240
  • [email protected]

Admission Enquiry 2020

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